1. Technical Field
Exemplary embodiments of the present invention relate to a method of fabricating a semiconductor device and, more particularly, to a method of forming patterns.
2. Description of the Related Art
As semiconductor devices become more highly integrated and their design rules shrink, the size of their hole patterns shrink as well. As their design rules continue to shrink, patterning technology for overcoming limitations in the resolution of currently used exposure equipment is required.
Various patterning technologies are being used to form hole patterns. For example, a single patterning technology and a double patterning technology (DPT) are being used.
The single patterning technology is used for forming hole patterns by a photolithography process that is well known in the art. However, with the single patterning technology, it is difficult to form fine hole patterns, due to limitations in the resolution of exposure equipment.
The double patterning technology may form patterns with a fine width and a fine pitch by selectively combining a plurality of hard mask layers and a spacer patterning technology (SPT). However, in the double patterning technology, processing becomes complicated, the number of process steps increases, high costs are incurred, and overlay issues occur.